28 Comments

  1. nix

    Hi I am using a Virtex 7 board and performing a 64 bit ripple carry addition. Can any one help me how do I use chipscope along with this program of mine. I cannot assign UCF s to inputs or outputs I think as there will be 129 inputs for the 64 bit additions between a and b and the carry and 65 outputs for the sum and carry out. How am I supposed to trigger the cores and not use UCF and check the working on Chip Scope using FPGA

    Reply
  2. mahi

    i want to see the out put of my adc on chip scope.I have clk2 as a divided clock which i am using as a clock to adc and i hav 10 bit signal as output.I am ot getting which signal to be connected to trigger.I have connected clk2_buf to clk port and my signal to trigger and set the data port same as trigger but i am not getting the output waveforn ..Can me please help me with this.

    Reply
    • Elecrom

      May be problem with a clock. Or design is not functioning at all. Try simulating the design first.

      Reply
  3. Mohan

    sir i have 2 problems in spartan 3e using xilinx 10.1
    1. I cant change the trigger width
    2. After press play button it’ll take more time to upload waveform and the sample %ge is at 0 only.

    Reply
  4. satish

    for the below comment……………..
    It is not coming as clock signal,it is coming always high signal…….

    Reply
    • Elecrom

      You cannot see the sampling clock in the chipscope. If you wish to see the clock signal itself, then, use the DCM to generate a clock signal which is twice (or even multiple) of the frequency of clock signal you want to observe. Then use this signal as a chipscope clock. You cannot measure time period from chipscope directly. Each time sample in the chipscope corresponds to one time period of the chipscope clock.

      Reply
  5. satish

    I tried to see input clk in chip-scope pro wave window,but it is coming as clock signal.Why? In chip-scope pro we are not able to see input clock signal??
    If we want to measure the clock frequency of input signal,how to measure the frequency?

    Reply
  6. sumit darak

    Excellent tutorial…Thanks a lot :)

    Reply
  7. VHDL Student

    Awesome!

    Reply
  8. Dave

    …job well done!!

    Reply
  9. mavi

    Sir can i know deferent between .cdc file,.ucf file,.bit file?

    Reply
  10. debolina

    i am new in using chipscope pro, ur tutorial help me a lot.sir, can i watch the output of adc on spartan 3e using cipscopepro? if so,then how? plz help me giving ur suggestion and helpful document or link from where i will learnt thanks in advance sir.

    Reply

  11. Mukunda

    The instructions are very clear!! Things worked at very first attempt.

    Thanks,
    Mukunda

    Reply
  12. Ammar

    So clear tutorial. Good job

    Ammar

    Reply
  13. Ravi

    Thanks a lot. Very well documented.

    Reply
  14. ABDULLAH GILL

    i m unable to see the waveform on SPARTAN 3E XC3S500 .
    CAN U KINDLY TELL WHERE THE PROBLEM IS?
    I LL BE VERY MUCH THANKFULL TO U.

    Reply
    • Elecrom

      please check your email.

      Reply
      • ABDULLAH GILL

        i m having difficulty in understanding why u have use trigger width of ‘8’ for the second trigger port? we may have used 6 as we had 6 signals to see.
        2nd problem is what the waveform is showing to us?it is a littel bit confusing?
        i hope u dont mind my silly questions .
        waiting for ur reply.
        GOD BLESS U

        Reply
        • Elecrom

          – Yes, you can very well use the width of ‘6’. What I have shown is just one example. You can use suitable width according to your requirement. – What waveform chipscope shows ? Ans : Chipscope will sample the trigger ports on positive clock egde and show you the output waveform. Whatever you see at the output is basically plot of all such samples collected on the posedge of clk. It doesn’t show you what happens in-between two clock edges and it is not possible to do that using chipscope.

          Reply
  15. abdullah

    hi thanks for the tutorial its really very easy but i m having problem with it while capturing data on analyzer i m using spartan 3e starter kit.can u please help me out of this?

    Reply
    • Elecrom

      which analyzer u r using ?

      Reply
      • ABDULLAH GILL

        i m using v10.1 of xilinx .
        how can i use chipscope pro in my design of OFDM. do i need to make some ammendments or just follow the above steps….
        anxiously waiting for ur reply.

        Reply
  16. Santosh

    Thanks for the tutorial. Easy to follow and effective.

    Reply
  17. Charles

    Excellent tutorial. I am an independent contractor and I have a client who is interested using the Xilinx Virtix5 in an FPGA design. What tools do I need to input the the state diagram and input into a state machine. Is there a program that can take the state machine and cover it into a timing diagram?

    Thanks

    Reply
    • Elecrom

      Hi,

      I didn’t get what exactly you want to do. There are some tools available which can realize the state machine from state diagram, but they are highly expensive.

      If you have complete description of the system and its state (or the state diagram), it is simple to implement the state machine directly by writing verilog code. Time required to do the implementation depends on the complexity of state diagram.

      Reply
  18. Aaron

    Excellent. Thanks.

    Reply

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